The present invention generally relates to non-volatile (permanent) memory-based mass storage devices suitable for use with computers and other processing apparatuses. More particularly, this invention relates to mass storage devices that use combinations of non-volatile solid-state memory components to promote the performance and endurance of the storage device.
Mass storage devices such as advanced technology attachment (ATA) drives and small computer system interface (SCSI) drives are rapidly adopting non-volatile solid-state memory technology, such as flash memory or another emerging solid-state memory technology, non-limiting examples of which include phase change memory (PCM), resistive random access memory (RRAM), magnetoresistive random access memory (MRAM), ferromagnetic random access memory (FRAM), organic memories, or nanotechnology-based storage media such as carbon nanofiber/nanotube-based substrates. Currently the most common solid-state technology uses NAND flash memory components (integrated circuits, or ICs) as inexpensive storage memory, often in a form commonly referred to as a solid-state drive (SSD).
Briefly, flash memory components store information in an array of floating-gate transistors (FGTs), referred to as cells. The cell of a NAND flash memory component has a top gate (TG) connected to a word (or control) line and juxtaposed to a floating gate (FG), the latter being sandwiched between the top gate and the channel of the cell. The floating gate is separated from the channel by a layer of tunnel oxide. Data are stored in (written to) a NAND flash cell in the form of a charge on the floating gate which, in turn, defines the channel properties of the NAND flash cell by either augmenting or opposing a charge on the top gate.
Data are erased from a NAND flash cell by applying an erase voltage to the device substrate, which then pulls electrons from the floating gate over an extended period of time. Charging (programming) of the floating gate is done by applying short pulses of a high positive voltage (typically 18-20V) to the word line that is connected to the top (programming) gate. The resulting electrical field draws electrons from the substrate through the tunnel oxide layer into the floating gate until the desired level of charge of the floating gate is achieved and verified by a subsequent read of the cell's bit value. The physics behind both programming and erasing are referred to as Fowler Nordheim quantum-mechanical tunneling, as well as injection of electrons into the floating gate.
From the above description it should be clear that the programming can only change the charge of any given floating gate from a fully erased state towards a fully programmed state, which is often described as the unidirectional programmability of NAND flash cells. That is, any NAND flash cell will have a fully erased state that, by convention, is equivalent to a “1” value of the stored bit and it is possible to program the cell thereafter to a “0” bit value but not vice versa. In multi-level cell (MLC) NAND flash memory components, more than two levels of charge are injected into the FG, allowing n bits per cell as long as 2n charge levels of the floating gate can be reliably resolved within a predetermined range of possible control voltages applied to the control gates to turn the gate ON. Similar to single-level cell (SLC) NAND flash memory, naming practices have been adopted for identifying the erased and programmed states of an MLC NAND flash memory cell. As an example, in the case of an MLC flash memory having four different levels to encode two bits per cell, possible bit values are “11” (fully erased), “10” (partially programmed), “01” (partially programmed), and “00” (fully programmed). However, as mentioned above, programming can only shift cells to a lower value, and programming in the opposite direction is not possible.
On a higher level, NAND flash cells are organized in the form of pages. Specifically, NAND flash memory components typically use thirty-two serially connected FGTs as the smallest unit where each FGT defines a memory cell. Several of these daisy chains form a page wherein the number of chains is always a power of two. NAND flash memory pages, in turn, are combined into memory blocks. Each block is a predetermined section of the NAND flash memory component. A NAND flash memory component allows data to be stored and retrieved on a page by page basis, in some cases even on a fraction of a page called sub-page. These may be referred to as the smallest functional or writable unit of the memory component. However, the use of sub-page programming typically results in a severe performance hit and is not commonly used in high performance devices. On the contrary, a common practice is to write two pages simultaneously of two different dies stacked to constitute an upper and lower plane. As a result, the physical page size is effectively doubled, which means that each access will read or write twice the number of data from or to the flash array. At the same time also the minimum amount of data that have to be written in a single sweep is doubled, for example in the case of a physical 8 kB flash page size, the accessible page size will be 16 kB.
Erasing NAND flash memory can only be done on a block-by-block basis. For example, erasing cells is done by connecting all FGT daisy chains within a block via a select transistor to an erase voltage of typically +20 V while connecting the other end of the chains via a second select transistor to ground. A simplified description of this process would be the application of a positive voltage to the device substrate on a per block basis. Since all pages are a serial daisy chain of FGTs, the erase current flows through all FGTs and consequently, the erase process does not allow isolation of individual cells. Moreover, for the purpose of simplicity of the design, NAND flash memory ties all pages within a block to a common erase switch, therefore, erasing of NAND flash memory cells can only be done on a per block basis. As a result, the minimum erasable size is an entire block, and, therefore every time a cell is being re-written, the entire block needs to be erased.
Over time, NAND flash memory cells wear out. Fowler-Nordheim tunneling, which is responsible for injecting electrons into the floating gate by drawing them from the substrate and through the tunnel oxide layer during programming as well as the reverse process of drawing the electrons from the floating gate back through the tunnel oxide layer and into the substrate during erasing, is extremely harsh on the tunnel oxide layer. The electrical fields that are applied are on the order of 10 million V/cm which can cause breaking of atomic bonds in the oxide layer, and consequent trapping of electrons at the broken atomic bond sites. An exacerbating factor in this context is the problem that the tunnel oxide layer becomes thinner and, by extension, more fragile with every migration to a new and smaller manufacturing process node. As a consequence, write endurance that used to be 10,000 program/erase (P/E) cycles at a 65 nm process geometry has decreased to about 3000 to 5000 P/E cycles at 30 nm process node and continues to decline towards roughly 1000 P/E cycles at 2× nm process nodes. Limited life span and endurance of NAND flash memory are becoming extremely critical factors in any considerations of NAND flash-based storage media.
As used herein, the endurance of a memory component refers to the endurance of its memory cells, which is typically quantified as the number of program/erase cycles a cell can be subjected to before it becomes unreliable. Accordingly, the remaining endurance of a NAND flash memory component depends on the endurance of its NAND memory cells. The endurance of a particular NAND cell is dependent on the number of P/E cycles that the cell has been subjected to. In addition, the level of programming plays an important role for the stress that a given cell has been exposed to. If cells are programmed to a higher level, that means that more electrons have passed through the oxide layer. In contrast, if cells are programmed merely to a “1” level, that means that they stay at the fully erased level and no electrons are drawn through the oxide layer, nor are electrons drawn “back” through the oxide layer on the next erase cycle. It should be apparent that this level of programming has less adverse effects on the tunnel oxide layer than a fully programmed level and subsequent erase.
Lastly, the frequency of program/erase cycles has a pronounced impact on the overall endurance of a NAND flash memory component since the oxide layer is “self-healing.” That is, after a given amount of time, the above mentioned broken atomic bonds that trap electronic charges re-anneal, thereby releasing the trapped electrons and rejuvenating the oxide layer in a somewhat temperature-dependent manner. Consequently, relative to this issue is whether the data of NAND flash cells have been recently accessed and/or are subjected to a high frequency of updates (referred to herein as “hot” or “fresh”) or whether the last access of the data dates back far enough and/or updates occur at a sufficiently lower frequency to allow the data to be considered as old (referred to herein as “cold” or having “cooled off”).
In view of the inherent endurance limitations of NAND flash memory that cannot be further improved by internal management of write accesses, for example, wear leveling, it is desirable to find ways to reduce the overall number of program/erase cycles a memory cell is subjected to. Further, it is desirable to reduce the program/erase frequency of any given NAND flash memory cell in order to allow recovery of the tunnel oxide layer and accordingly increase the endurance of the NAND flash memory component as a whole.